Centering arrangement for a ternary coder

ABSTRACT

A CALIBRATION VOLTAGE IS PERIODICALLY COUPLED TO A FEEDBACK COMPARISON TERNARY CODER DURING CALIBRATION TIME TO GENERATE A TENARY CALIBRATION CODE OF ALL TENARY 1 DIGITS WHEN THE CODER IS PROPERLY CENTERED. AN ARRANGEMENT EXAMINES EACH TENARY DIGIT STARTING FROM THE MOST SIGNIFICANT DIGIT TO DETECT A DEVIATION FROM THE DESIRED CALIBRATION CODE REPRESENTED BY THE FIRST TENARY DIGIT DIFFERENT FROM TENARY 1 AND APPROPRIATELY ADJUSTS THE REFERENCE VOLTAGE OF THE CODER TO COMPENSATE FOR THIS DEVIATION.

United States Patent [72] Inventors Michel L. Avignon [56] References Cited "willy-SWd", f f UNITED STATES PATENTS 21 A i No 332.?" Made" 3,032,15 5/1962 Villars 340/347 I 1 3,365,7l3 1/1968 Avignon et al 340 347 {22] PM 1967 3 210 528 10/1965 Magill et al 340/347x Patented June 28, I971 [731 Assignee International Standard Electric Primary Examiner-Maynard R. Wilbur Corporation Assistant Examiner-Michael K. Wolensky New York, AlwrneysC. Cornell Remsen, Jr., Rayson P. Morris, Percy [32] Priority Jan. 12, 1967 P. Lantzy, Philip M. Bolton and Isidore Togut {33] France [3 l] 90.86!

ABSTRACT: A calibration voltage is periodically coupled to a feedback comparison ternary coder during calibration time to [54] CENTERING ARRANGEMENT FOR A TERNARY generate a ternary calibration code of all ternar 1 digits when CODER Y 10 cl 9 D the coder is properly centered. An arrangement examines anus rawmg each ternary digit starting from the most significant digit to de- [52] U.S. Cl 340/347 tect a deviation from the desired calibration code represented [5 l] [103k l3/24 by the first ternary digit different from ternary 1 and ap- Field of Search 340/347 propriately adjusts the reference voltage of the coder to com- (A/D), 347 pensate for this deviation.

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sum 3 [IF 3 Inventors MICHEL L. AVI GNON JOSEP L. M4067? BACKGROUND OF THE INVENTION This invention relates to ternary coders and more particularly to an automatic centering arrangement for feedback comparison ternary coders to increase the accuracy thereof.

In a feedback comparison coder, whether it is a binary coder, a ternary coder or decimal coder, a sequential series of comparisons are made between the analog voltage to be coded and a voltage delivered by a decoder for determining successively the digits of the code number in a decreasing weight order.

In such a coder the same number No, which will be called "check or calibration code, must be obtained each time a calibration voltage 2 is coded. This does not happen in practice due to the variations of the DC voltages added to the analog signal to be coded and variations of the component characteristics so that the number obtained in coding the calibration voltage differs by a quantity of A N from the nominal value 0. It can be stated that the accuracy of the coder increases as the maximum value of the deviation A N is decreased.

SUMMARY OF THE INVENTION In accordance with the present invention, the deviation is reduced by means of a feedback loop in which, after having determined the sign of the deviation obtained by coding the calibration voltage the amplitude of one of the DC voltages is corrected periodically, the direction of the correction being such that the deviation is reduced. This is referred to as centering correction for the coder. The amplitude c of the calibration voltage ranges between the voltages 0 and Be which defines the range of coding and, when the checking code obtained by coding this signal e is determined, the sign of the deviation is obtained by comparison or by subtraction. In the case of a binary code, if e,,=Ec/2, the check code or calibration code No (which comprises n digits) can indifferently present one ofthe values 2"-' I or 2"". Since allthe numbers ofthe value lowerthan or equal to 2'" l have a digit of rank I equal to 0 and all the numbers of value higher than or equal to 2"" have a digit of rank 1 equal to I, the sign ofthe deviation is obtained by examining the value of this digit.

In the case ofa ternary code, the procedure is different. For instance, if e,,=Ec/2 and n=4 then the code I I l l is obtained fora deviation lower than :l/Z Q (0 being the value of one quantizing step); the code IIIO or lll2 is obtained for a deviation ranging between :I/Z Q and 11.5 0; and the code ll00, lIOl, N02, or H20, H21, H22 is obtained for a deviation ranging between 11.5 Q and :2.5 0 etc.

In order to determine the sign of the deviation, it is thus necessary to examine all the pairs of binary bits with each pair of binary bits representing a ternary digit starting from that pair of binary digits which represents the most significant ternary digit. Thus, for a deviation higher than 1-2.5 Q, the deviation sign is given by the value of the ternary digit of rank 3.

An object of the present invention is to provide an automatic centering arrangement for a feedback comparison ternary coder which corrects periodically the centering of the ternary coder in order to minimize the effect of the variation of DC voltages and of the components in the coder.

A feature of this invention is the provision of an automatic centering arrangement for a feedback comparison ternary coder comprising first means to periodically couple a calibration voltage to the coder during calibration time for providing a given ternary calibration code when the coder is properly centered; and second means coupled to the coder to detect a deviation from the given calibration code during the calibration time and adjust the coder to compensate for the deviation.

Another feature of this invention is the provision that a calibration signal having an amplitude equal to half the maximum amplitude of the coding range is applied to the coder which if properly operating will produce a check or calibration code which, expressed in ternary code, must comprise only l's. An arrangement is provided to successively examine all the digits of the code being produced from the calibration voltage starting from the most significant ternary digit with the direction of the deviation being given by the value of the first digit different from ternary l and that the said deviation is corrected by modifying the value of the reference voltage used for coding, this voltage being increased if the ternary digit is in condition 2 and decreased if this digit is in ternary condition 0.

BRIEF DESCRIPTION OF THE DRAWING The above mentioned other features and objects of this invention will become apparent by reference to the following description taken in conjunction with the accompanying drawings, in which:

FIGS. la to le illustrate a number of logical symbolsutilized in the block diagrams of FIGS. 4 and 5;

FIG. 2 illustrates a diagram of voltages in a first mode of comparison;

FIG. 3 illustrates a diagram of voltages in a second mode of comparison;

FIG. 4 illustrates a block diagram of the centering arrangemcnt for a feedback comparison type ternary coder in accordance with the principles ofthis invention; and

FIG. 5 is a block diagram ofthe centering circuit of FIG. 4,

DESCRIPTION OF THE PREFERRED EMBODIMENT Before describing the invention, logical algebra notations will be discussed which will be used herein in order to simplify the description of the logical operations. The subject is treated extensively in numerous papers and in particular in the book Logical Design of Digital Computers" by M. Phister (J. Wiley publisher).

Thus, if a condition characterized by the presence of a signal is written A, the condition characterized by the absence ofsaid signal will be written A.

These two conditions are linked by the well known logical relation A XA=0, in which the sign X is the symbol ofthe coincidence logical function or AND function.

If a condition C appears only if the conditions A and B are simultaneously present, the logical expression is AXB=C and this function may be carried out by means of a coincidence or AND gate.

Il'a condition C appears when at least one oftwo conditions E and F is present, the logical expression is E +F=C and this function is carried out by means ofa mixing gate or OR gate.

Referring to FIGS. la to Ie, the meaning of some symbols used in the block diagrams of FIGS. 4 and 5 are described.

FIG. la represents a simple AND gate.

FIG. lb represents a simple OR gate.

FIG. lc represents an INHIBIT gate having two input terminals 911', 91g, and which is blocked when a signal is applied over the inhibit input 91]".

FIG. Id represents a bistable circuit or flip-flop to which a control signal is applied over one of its input terminals 92-1 or 92-0 in order to set it in the I state or to reset it in the 0 state. A voltage of same polarity as that of the control signals is present, either on the output 93I when the flip-flop is in the I state, or on the output 93-0 when it is in the 0 state. If the flip-flop is referenced B1, the logical condition which characterizes the fact that it is in the I state will be written BI and thasharacterizing the fact that it is in the 0 state will be written BI.

FIG. Ie represents an electronic gate which, when activated by a signal applied to its input terminal 91a, transmits the amplitude of the signal present on the terminal 91b to terminal 91c.

In feedback comparison coding, the value of each digit is successively determined starting from the most significant digit. Thus, the coding of one sample is performed, for a n digit ternary number, in n ternary digit time slots. If the condi tions of the ternary digits 0, I, 2 are represented, by way of a nonlimitating example, by the pairs of binary bits 01, 00, 10, each ternary digit time slot is subdivided into two binary digit time slots for determining the value of each one of the ternary bits. The binary digit time slots reserved to the ternary digit of rank l are referenced mll, ml2; the binary digit time slots reserved to the ternary digit of rank 2 are referenced m2l, m22; etc... Thus. the j" ternary digit time slot is divided into two binary digit time slots referenced mjl and mj2, where for n= ternary code digitj can be equal to l, 2, 3, 4 or 5. Finally each binary digit time slot is divided into four basic time slots 0, b, c, d.

FIG. 2 shows that the most significant ternary digit divides the total coding range of amplitude Ed into three subranges, and it is realized that the next less significant digit divides each subrange into three equal pans, etc...

At the time m1l.a (basic time slot 11 ofthe binary digit time slot mll), which defines the beginning of the coding of the sample ecl represented on FIG. 2, all the flip-flops of one register which comprises 211 flip-flops (register RG, FIG. 4) are set to the 0 state with the exception of the most significant one which is set to the I state. At times mlLb and mll. c the decoded voltage edl (FIG. 0) is compared to the signal ecl, this voltage edl being supplied by decoder DC (FIG. 4) coupledtoregister RG.lf,asin thecase of FIG. 2, ecl-edl Z 0,(information supplied by comparator CM, FIG. 4) the most significant ternary digit is in condition 2 (pair of binary bits and the state ofthe flip-flops which display this number is not modified. If one has ecl edl O, the most significant flipflop of the register is set to the 0 state at the time ml I.c under the control of the logical control unit LU (FIG. 4) and a new comparison is made at time ml2.b and m l2.c. If ecl -ed] 3 0, the most significant ternary digit is in-condition I (pair of binary bits 00) and the state of the flip-flops is not modified. Last, if ecl edl 0, the second flip-flop is set to the I state at the time ml2.c, so that the ternary digit is in condition 0 (pair of binary bits OI At the time ml2.d, the two most significant flip-flops show the final value ofthe ternary digit of rank l.

The same operations are carried out at the following ternary digit time slots for the determination of the ternary digits of decreasing weights and at the time mn2.d, the code corresponding to the voltage ecl is shown in the register.

TABLE 1 below groups these different operations for the determination of the ternary digits of rankj at the times mjl and mj2, the two flip-flops being referenced Bjl and Bj2. In the second column, the expression conditional" means that the command depends upon the result ofthe comparison.

TABLE I Exact Value of I binan 'ILtnc Flip Flop command Comparison bit mjLa Bjl in the 1 state mjLb .1 m)l.c Bil in the Qstate (c0nditional) m]l.d X mj2.a mjlb l nij2.c BjEin th -t )statc t'coiiditionaltnuj l mild X When alternating voltages of amplitude ec ranging between zero and t Ed/2 volts (see FIG. 3) are to be coded, ecl Ed/2 +ec (the voltage ec may be positive or negative) so that the inequality ecl edlZ 0 (1) becomes:. Ed/Z +ec-edl2 0 or edl ec S Ed/Z (2).

Last, it will be noted that, ifthe complement of the number written in the register is decoded, the output voltages is ed=ED -edl (see FIG. 3) and that the inequality l becomes:

viz.: ec-l-ed Z Ell/2 (3).

It is thus seen that both procedures corresponding to the inequalities(2 and (3), involve a comparison at a level Ed/Z different from zero, thus enabling the operation of said comparator at a constant level.

The centering correction consists then in adjusting periodically the amplitude U of a reference voltage of rated value E'd/Z according to the sign ofthe deviation.

For a calibration voltage e =0, there must be obtained, in a five digit ternary code, the control or calibration code No. =1 l l l I. For a very small deviation the less significant digit is in condition 0 or 2. The obtaining of a digit in condition 0 instead of a digit in condition 1 means that the voltage e is too small, or that the voltage U may be considered as too high, by including in this voltage the variation of the DC voltages added to the signal ec and the variations of the components. The centering correction will, thus, consist in reducing the voltage U when a digit in condition 0 is detected, and to increase it when a digit in condition 2 is detected.

FIG. 4 illustrates a block diagram of a feedback ternary coder incorporating an automatic centering correction arrangement in accordance with the principles of this invention. This coder comprises clock CU, register RG, decoder DC, incoming circuit NP, comparator CM, centering correction circuit CC, and logical control unit LU.

Clock CU delivers the following signals:

a. coding time signals defining the time interval reserved to the coding ofa sample into an n-digit ternary number. Ifa time multiplex coding of the signals received over (.r l) analog channels is considered, the clock must deliver s signals VI to Vs, the signal Vs defining the calibration time which may also be used for the transmission ofa synchronization code; and

b. digit time slot signals ml 1, m12, mn2, and basic time slot signals a, b, c, d, defined previously.

Register RG comprises 2n flip-flops to store the n pairs of binary digits representing the n ternary digits.

Digital to analog decoder DC is coupled to register RG and supplies the decoded voltage edl or ed (FIG. 3). Such a decoder for ternary codes has been'described in the copending application of M. L. Avignon and J. L. Mader, Ser. No.

692,929, Filed Dec. 22, I967.

Incoming circuit NP receives the input voltages (ec) to' during the times V1 to V(sl) and the calibration voltage e =Ed/2 during the time Vs. This circuit assures the holding, during the coding time, of the amplitude of the sample ec corresponding to one channel.

Comparator CM delivers signals controlling the setting to the I state or to the 0 state ofthe decision flip-flop BD according to the result of the comparison. It will be noted that the fact that the inequality (2), or the inequality (3), is fulfilled means, at time mjl (see TABLE I), that the determined binary bit is 1 whereas at, time mj2, this condition means that the determined binary bit is 0. It is thus necessary to reverse the inputs of the flip-flops at each digit time slot in order that the fact that it is in the I state (or in the 0 state) means that the digit tested must be kept (or complemented). This switching is represented in FIG. 5. In these conditions, the state of the flipflop represents, at the basic time slot d of each binary digit time slot, the value of the determined binary bit and the code is thus available in series form.

Centering correction circuit CC examines, at time Vs, successively the value to each ternary digit starting with the most significant ternary digits up to the time where one of these digits is in a condition different from I. At this digit time slot, the sign of the deviation is given by the condition 0 or 2 of the ternary digit. This information enables the generation of a signal which is applied to comparator CM in such a way as to modify the amplitude of the reference voltage U.

Logical control unit LU controls the flip-flops of register R0 in relation to the state of flip-flop BD and according to the rules which have been stated hereinabove.

FIG. 5 illustrates the detailed block diagram of decision circuit DE comprising flip-flop BD (FIG. 4) and centering correction circuit CC. In circuit DE, gates P5 to P10 assure the switching on the inputs of the flip-flop BD, alternatively, to store the fact that the inequality (2) or (3) is fulfilled, meaning that the condition of the digit determined is l or 0. This last case appears during an even digit time slot, characterized by the logical condition: Mp==ml2 +m22 +m32 +m42 +m52 set up in the circuit 8? of FIG. 5, an od d ligit time slot being characterized by the logical condition Mp. Flip-flop ED is appropriately activated during the time of each ternary digit by gates P5 to P8 under control of the timingsignal (mjl )c.

It is thus seen that, for the condition Mp Xc, the outputs and (l) of comparator CM are applied respectively to the inputs 0 and l of flip-flop BD and that. for the condition M pXc, they are applied respectively to the inputs 1 and 0 of this flipflop. The flip-flop BD shows, at each basic time slot d, the value of the binary bit determined at this time, this information being available on conductor A.

Centering circuit CC comprises delay circuit RC, binary pair selection circuit 8?, and adjustment circuit RV.

Delay circuit RC comprises flip-flops BD' and BE controlled from flip-flop BD by means of electronic gates P1 to P4. More precisely. the electronic gates P1 and P2 are activated at the time d for each (mjl) time slots enabling the transfer of the state of flip-flop BD to flip-flop BD' and, at the ple and no as a limitation to the scope of our invention as set forth in theobjects thereofand in the accompanying claims.

We claim: 1. An automatic centering arrangement for a feedback comparison ternary coder comprising:

first means to periodically couple a calibration voltage to said coder during calibration time for providing a given ternary calibration code when said coder is properly centered, said calibration code including a plurality of ternary digits each having a given condition; and

time c for each (mj2) time slots, electronic gates P3 and P4 second means coupled to said coder to detect a deviation control the transfer from flip-flop 8D to flip-flop BE. 11, for from said given condition of each one of said plurality of instance, the infonnation received from the comparator CM is ternary digits of said given calibration code during said considered at the digit time slot mll (i=1 it is seen that, in calibration time and adjust said coder to compensate for ml2.d, flip-flops BE and 8B show the values of the two bisaid deviation. nary bits representing the most significant ternary digit. When 2. An arrangement according to claim 1, wherein: i=2, 3, 4, and 5. flip-flops BE and BD' will show the value of said given calibration code includes a plurality of ternary l the binary digits representing the other ternary digits. digits; and

Binary pair selection circuit BP delivers a signal Bb for the said second means includes third means coupled to said logical condition Bb=BaVs MpXd. coder to sequentially examine the condition ofeach digit Adjustment circuit RV for the reference voltage controls a of said coded calibration voltage from the most signifimodification of the voltage U at the terminals of condenser C cant ternary digit to the least significant ternary digit; in relation with the value of the ternary digits used. To this effourth means coupled to said third means to detect the first fect flip-flq Ca is set to the 1 state for the logical condition digit of said coded calibration voltage deviating from ter- Bb BD'XBE (pair of binary bits l0.temary condition Zl.and nary l and produce a control signal in response to said flip-flop Cb is set to the I state for the logical condition deviation; and BbXEE'XBE (pair of binary bits (ll. ternary condition 0). fifth means coupled to said fourth means and said coder This centering correction circuit operates as follows: at the responsive to said control signal to adjust said coder and beginning of the calibration time, in V.r.m1l, flip-flops Ca and compensate for said deviation. Cb are set to the 0 state, and flip-flop Ba is set to the I state. At 40 3. An arrangement according to claim 2, wherein: each of the following times ml2.d, m22.d, m32.d, m42.dand fifth means includes a source of reference voltage for said 0152.5, circuit BP delivers a signal Bb which is applied to one coder; and of the inputs of the two AND circuits which control flip-flops sixth means coupled to said fourth means and said source Ca and Cb. If at any of these times one of the binary bits writresponsive to said control signal to adjust the value of said ten in flip-flops BE and BB is different than 0, one of these reference voltage to compensate for said deviation. flip-flops sets to the 1 state as it has been seen hereinabove 4. An arrangement according to claim 3, wherein: and flip-flop Ba is set to the 0 state by the logical condition Ca said source includes a capacitor; and Xa+bXu. The three possible logical conditions are said sixth means includes seventh means coupled to said represented in column 1 of TABLE II hereinbelow, the capacitor and said fourth means to control the charge and columns 2 and 3 representing, respectively, the condition of discharge of said capacitor depending upon the direction the pairs of binary bits and the corresponding ternary condiofsaid deviation. tion, 5. An arrangement according to claim 4, wherein:

TABLE II Pair of Voltages Diodes binary Ternary Logical Condition bits digit Ca Cb D1 D2 Charge of C 6;; H; oo 1 +20 0 Blocked.. Blocked Constant. Ca x Cb Di 0 0 0 Conductive .do. Decreases. C a x Cb l0 2 +2(,' +2U Blocked Conductive, Increases. l 2 3 4 5 6 7 8.

it will now be assumed that flip-flops Ca and Cb are made said seventh means includes a first bistable device coupled with PNP transistors supplied by a voltage source ofamplitude Said fourth means and Said capacitor; and Ed. Capacitor C is connected to the 0 output of flip-flop Ca 8 Second bistable device coupled to said fourth means and and to the 1 output of flip-flop Cb through diodes D1, D2 and said capacitor; resistors R1 and R2, so that the voltages applied t o said coneach of said bistable devices being in the 0 condition when denser are taken, respectively, over the outputs Ca and Cb of aid Control signal indicates a ternary 1, these flj .flo as i di d i columns 4 d 5 of TABLE ll, one of said bistable devices being set to 1 when said control Columns 6 and 7 show the conduction state of diodes D1 and gn l indi es a ternary 2 to charge said capacitor, and D2 for three of the logical conditions defined by the two flipthe other of said bistable devices being set to I when said flops and column 8 indicates the direction of variation of the control signal indicates a ternary 0 to discharge said charge of condenser C according to the established logical capacitorv condition. It is seen that the charge of this condenser An rrangement according to claim 1, wherein; decreases when the ternary condition 0 is detected and inid rin l a ur of fer l ag nd creases when the ternary condition 2 is detected, and that the average value of the voltage at the terminals of the condenser is U Ed /2.

said second means is coupled to said source to adjust the value of said reference voltage to compensate for said deviation.

7. An arrangement according to claim 1, wherein:

each condition of each ternary digit is represented by a different pair of binary digits;

said given calibration code includes a plurality of ternary l digits each being represented by the pair of binary digits and third means coupled to said coder to sequentially examine each of said pairs of binary digits of said coded calibration voltage from that pair of binary digits representing the most significant temary digit to that pair of binary digits representing the least significant ternary digit;

fourth means coupled to said third means to detect the first pair of binary digits of said coded calibration voltage deviating from 00 and produce a control signal in response to said deviation; and

fifth means coupled to said fourth means and said coder responsive to said control signal to adjust said coder and compensate for said deviation.

8 An arrangement according to claim 7. wherein:

said fifth means includes a source of reference voltage for said coder, and

sixth means coupled to said fourth means and said source responsive to said control signal to adjust the value of said reference voltage to compensate for said deviation.

9. An arrangement according to claim 8, wherein:

said source includes a capacitor; and

said sixth means includes seventh means coupled to said capacitor and said fourth means responsive to said control signal to charge said capacitor when said control signal represents a pair of binary digits ]0 and to discharge said capacitor when said control signal represents a pair of binary digits 0].

10. An arrangement according to claim 9, wherein:

said seventh means includes a first bistable device coupled to said fourth means and said capacitor; and

a second bistable device coupled to said fourth means and said capacitor;

each of said bistable devices being in the 0 condition when said control signal indicates the pair of binary digits 00,

one of said bistable devices being set to I when said control signal indicates the pair of binary digits l0 to charge said capacitor; and

the other of said bistable devices being set to I when said control signal indicates the pair of binary digits 0] to discharge said capacitor. 

